A Nonspeculative Maximally Redundant Signed Digit Adder

Signed digit number systems provide the possibility of constant-time addition, where inter-digit carry propagation is eliminated. Carry-free addition for signed digit number systems is primarily a three-step process. However, the special case of maximally redundant signed digit number systems leads to more efficient carry-free addition. This has been previously achieved by speculative computation of digit-sum values using three parallel adders. We propose an alternative nonspeculative addition scheme that computes the transfer values through a fast combinational logic. The proposed carry-free addition scheme uses a combinational logic, to compute the transfer digit, and the equivalent of two adders. The simulation and synthesis of the two previous works and this work based on 0.13 μm CMOS technology shows that the proposed circuit operates faster and has a lower product of delay × power.